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| INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC * The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4040B MSI 12-stage binary counter Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification 12-stage binary counter DESCRIPTION The HEF4040B is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (O0 to O11). The counter advances on the HIGH to LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of CP. Each counter stage is a static toggle flip-flop. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. HEF4040B MSI Fig.1 Functional diagram. PINNING CP MR O0 to O11 clock input (HIGH to LOW edge-triggered) master reset input (active HIGH) parallel outputs APPLICATION INFORMATION Some examples of applications for the HEF4040B are: * Frequency dividing circuits * Time delay circuits Fig.2 Pinning diagram. * Control counters FAMILY DATA, IDD LIMITS category MSI HEF4040BP(N): HEF4040BD(F): HEF4040BT(D): 16-lead DIL; plastic (SOT38-1) 16-lead DIL; ceramic (cerdip) (SOT74) 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America See Family Specifications January 1995 2 Philips Semiconductors Product specification 12-stage binary counter HEF4040B MSI Fig.3 Logic diagram. AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns VDD V Propagation delays CP O0 HIGH to LOW 5 10 15 5 LOW to HIGH On On + 1 HIGH to LOW 10 15 5 10 15 5 LOW to HIGH MR On HIGH to LOW Output transition times HIGH to LOW 10 15 5 10 15 5 10 15 5 LOW to HIGH 10 15 January 1995 3 tTLH tTHL tPHL tPLH tPHL tPLH tPHL 105 45 35 85 40 30 35 15 10 35 15 10 90 40 30 60 30 20 60 30 20 210 90 70 170 80 60 70 30 20 70 30 20 180 80 60 120 60 40 120 60 40 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 78 ns 34 ns 27 ns 58 ns 29 ns 22 ns note 1 note 1 note 1 note 1 note 1 note 1 63 ns 29 ns 22 ns 10 ns 9 ns 6 ns 10 ns 9 ns 6 ns + + + + + + + + + + + + + + + (0,55 ns/pF) CL (0,23 ns/pF) CL (0,16 ns/pF) CL (0,55 ns/pF) CL (0,23 ns/pF) CL (0,16 ns/pF) CL (0,55 ns/pF) CL (0,23 ns/pF) CL (0,16 ns/pF) CL (0,55 ns/pF) CL (0,23 ns/pF) CL (0,16 ns/pF) CL (0,55 ns/pF) CL (0,23 ns/pF) CL (0,16 ns/pF) CL (1,0 ns/pF) CL (0,42 ns/pF) CL (0,28 ns/pF) CL (1,0 ns/pF) CL (0,42 ns/pF) CL (0,28 ns/pF) CL SYMBOL MIN. TYP. MAX. TYPICAL EXTRAPOLATION FORMULA Philips Semiconductors Product specification 12-stage binary counter HEF4040B MSI SYMBOL MIN. TYP. MAX. 50 tWCPH 30 20 40 tWMRH 30 20 40 tRMR 30 20 10 fmax 15 25 25 15 10 20 15 10 20 15 10 20 30 50 ns ns ns ns ns ns ns ns ns MHz MHz MHz see also waveforms Fig.4 TYPICAL EXTRAPOLATION FORMULA VDD V Minimum clock pulse width; HIGH Minimum MR pulse width; HIGH Recovery time for MR Maximum clock pulse frequency 5 10 15 5 10 15 5 10 15 5 10 15 Note 1. For other loads than 50 pF at the nth output, use the slope given. VDD V Dynamic power dissipation per package (P) 5 10 15 TYPICAL FORMULA FOR P (W) 400 fi + (foCL) x VDD2 2 000 fi + (foCL) x VDD2 5 200 fi + (foCL) x VDD2 where fi = input freq. (MHz) fo = output freq. (MHz) CL = load cap. (pF) (foCL) = sum of outputs VDD = supply voltage (V) January 1995 4 Philips Semiconductors Product specification 12-stage binary counter HEF4040B MSI Fig.4 Waveforms showing propagation delays for MR to On and CP to O0, minimum MR and CP pulse widths. January 1995 5 |
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